Interconnection Networks

same shape different rates figure


As processor cores on modern supercomputers have become faster, computations/floating point operations have become faster. However, the network latency and bandwidth have not improved proportionally. In addition to faster cores, increase in the number of cores per node is also stressing the network further. Therefore the cost of communicating data both on-node and off-node has become a critical factor affecting the overall performance of a parallel application. The goal of this project is to improve the communication and overall performance of parallel applications using interconnect topology aware task mapping.

There are several components of this work:

  • Study of inter-job interference
  • Characterization of parallel applications
  • Tools to profile the communication in parallel applications
  • Simulation and modeling of network contention
  • Algorithms for topology aware task mapping

Current funding: This project is currently funded by the Laboratory Directed Research and Development Program at LLNL (LDRD) under project tracking code 13-ERD-055 (STATE - Scalable Topology Aware Task Embedding).


CASC @ Lawrence Livermore National Laboratory

Parallel Programming Laboratory at
University of Illinois at Urbana-Champaign

  • Nikhil Jain

  • Laxmikant V. Kale

Other collaborators:

Greg Bronevetsky, Lawrence Livermore National Laboratory

William D. Gropp, University of Illinois at Urbana-Champaign

Torsten Hoefler, ETH Zuerich, Switzerland

Jeff Keasler, Lawrence Livermore National Laboratory

Adam Kunen, Lawrence Livermore National Laboratory

Katie Lewis, Lawrence Livermore National Laboratory

Peter Robinson, Lawrence Livermore National Laboratory