See the SC17 list of LLNL participants and the SC17 Event Calendar for a day-by-day schedule of LLNL’s sessions and Job Fair presence. During the conference, follow Computation on Twitter and other social media with hashtags #SC17 and #hpcconnects.
The twenty-ninth annual Supercomputing Conference (SC17) will begin on November 12 in Denver, Colorado. Dozens of attendees from Lawrence Livermore’s Computation Directorate will join industry leaders, application developers, program managers, journalists, and congressional staffers for the six-day conference focused on high performance computing (HPC).
SC17’s theme is HPC Connects. For Kathryn Mohror, a Livermore computer scientist, the opportunities that spring from face-to-face interaction are key. “SC is amazing because so many people come from all over the world to show off their HPC achievements from the last year,” she says. “It’s the one conference where I know I can find the latest information on any given HPC topic—and most likely straight from the person who is working on it.”
Ignacio Laguna, a computer scientist attending for the sixth time, looks forward to learning about new research on HPC programming systems, resilience, and correctness. “It is exciting to see the large number of new ideas that are discussed every year at SC,” he adds.
Twelve-time SC participant Abhinav Bhatele is eager to attend technical presentations and learn about innovations in exascale technology. “I have been to SC nearly every year since 2005. It is the premier international conference for HPC, enabling computer scientists to interact with vendors, meet with remote colleagues, and forge new collaborations,” he states.
A Busy Schedule
Like many of Computation’s SC17 attendees, Bhatele is responsible for several conference sessions as co-presenter of three papers and co-organizer of a workshop. The first paper focuses on a novel deep-learning based approach developed at Livermore that uses transfer learning to model performance and power consumption of HPC codes. Bhatele’s second paper showcases a multi-institutional collaboration in which researchers have created a general and scalable framework called ScrubJay to analyze large-scale HPC performance data from diverse sources.
Another paper describes advances in a simulation framework, called TraceR, that enables comparisons between different fat-tree network configurations—a common topology in HPC systems. “TraceR can be used to decide which network configuration is optimal for specific workloads when making network design or procurement decisions,” explains Bhatele.
Bhatele will also represent the Laboratory as a co-chair of SC’s Fourth International Workshop on Visual Performance Analysis, where participants will discuss advances in performance analysis and visualization tools. He notes, “The workshop aims to bring together researchers from the fields of visualization and performance analysis to create collaborations and build useful analytics and visualization tools for the HPC community.”
Launching a New Workshop
The increasing complexity of heterogeneous HPC systems poses significant software correctness challenges. As one of the Department of Energy’s leading HPC centers, Livermore strives to develop innovative approaches to correctness that anticipate exascale computing power. For instance, Laboratory scientists have created a tool for non-deterministic debugging of parallel applications as well as a program that automatically diagnoses performance and correctness faults in message passing interface applications.
Laguna and collaborator Cindy Rubio-González (University of California at Davis) have been working on HPC correctness solutions and bug detection. “We thought this area of research was underrepresented at SC, so we decided to propose a workshop with the expectation that new ideas in this area could be discussed at SC,” says Laguna. “The goal is to bring together researchers and developers to address the problem of correctness in HPC.”
The First International Workshop on Software Correctness for HPC Applications will debut on SC17’s opening day. Beginning with a keynote address, the workshop will feature seven presentations grouped into three categories: applications and algorithms correctness; runtime systems correctness; and code generation and code equivalence correctness. “We have a very interesting program. We hope that novel ideas will be developed out of the workshop with the goal of making HPC simulations more reliable,” states Laguna.
Several Computation staff serve on conference program committees as varied as Exhibits, Inclusivity, Tutorials, Papers, System Software, and Registration/Store/Merchandise. Mohror chairs the Data Analytics, Visualization & Storage (DAVS) committee, which is charged with selecting papers on these topics for the conference.
The committee members coordinate remotely to review each submitted paper, dividing up the work according to area of expertise. Mohror states, “After the reviews are submitted, we evaluate them for thoroughness and to determine whether we need to pull in additional expertise for a particular paper. Our goal is to conduct thorough reviews and obtain consensus from the committee on each paper as much as possible before the in-person meeting.”
After reviews are complete, the committee meets in person to decide which of the dozens of submitted papers should be included in the conference’s technical program. “The meeting lasts an entire day, and we ensure only high-quality, rigorously reviewed papers are included in the SC proceedings,” explains Mohror.
Acceptances and rejections follow, then the committee places papers into conference sessions according to common topics or themes. Mohror also leads the committee in assigning moderators for the DAVS paper sessions. “Our reviewers are experts in HPC topics related to DAVS,” she says. “We take the review and selection process very seriously.”